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Design and Implementation of Reversible Binary Comparator using reversible logic gates


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Family of Microcontrollers...!!

Posted by T P Kausalya Nandan
T P Kausalya Nandan
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on Sunday, 23 February 2014
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3D Transistors: Better Performance at Even Lower Power

Posted by K.Rambabu
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on Tuesday, 11 February 2014
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Technology has progressed quite swiftly, since one of the greatest inventions-transistor, paving way for more powerful, cost-effective and energy efficient products. For the first time in history, silicon transistors have entered the third dimension with the Tri-Gate transistors. Read on to find out it's features, structure and how it benefits the new-age processors.

So what comes to your mind when you hear the word 'Intel'? Definitely, a manufacturer of all your celeron's, pentium's, dual cores, core i's, and other micro-processor chips, right? The pace dictated by Moore's Law has required numerous innovations and as a result of which the 'Sponsors of Tomorrow' introduced a three dimensional transistor technology, which is basically, Tri-Gate transistors on its 22 nm logic technology.

Important Turning Point in Transistor Technology

In 1947, the first transistor was demonstrated at Bell Laboratories. Silicon was first used to produce bipolar transistors in 1954, but it was not until 1960 that the first silicon metal oxide semiconductor field-effect transistor (MOSFET) was built. The earliest MOSFETs were 2D planar devices with current flowing along the surface of the silicon under the gate. The basic structure of MOSFET devices has remained substantially unchanged for over 50 years.

Continued optimization and manufacturability studies on 3-D transistor structures was on at research and development organizations in leading semiconductor companies. Some of the process and patent development has been published and publicly shared, and some remained in corporate labs. The International Technology Roadmap for Semiconductors (ITRS) drives the research investment interests of the semiconductor industry, which is coordinated and published by a consortium of manufacturers, suppliers, and research institutes.

The ITRS defines transistor technology requirements to achieve continued improvement in performance, power, and density along with options which should be explored to achieve the goals. The ITRS and its public documentation captures conclusions and recommendations regarding manufacturing capabilities like strained silicon and High-K metal gate, and now the use of 3-D transistor technologies to maintain the benefits of Moore’s law. Based on documents produced by the ITRS and an examination of academic papers and patent filings, research into 3-D transistor technologies has grown dramatically in the last decade.

The Triggers That Threw Spotlight on 3-D Transistors

Two important pronouncements that have occurred in the last two years that have propelled the 3-D transistor structure into the industry spotlight, and into a permanent place in the technology story of MOSFET transistors are 1) The first announcement by Intel Corporation on 4th of May, 2011, about their Tri-Gate transistor design that had been selected for the design and manufacture of their 22 nm semiconductor products. 2) The second announcement was the publication of ITRS technology roadmaps, with contributions from many other semiconductor manufacturing companies that identified 3-D transistor technology as the primary enabler of all incremental semiconductor improvement beyond the 20 nm or 22 nm design node.

So Exactly How Small is 20 nano-meter?
Each and every micro-processor manufactured today is made of millions, or even billions, of tiny electrical components called transistors. Over time, in accordance with Moore's law, transistors have been getting smaller and smaller and because of which, computing and communication devices continue to get smarter, faster and highly efficient.

Intel believes that keeping up with Moore's Law has never been exactly easy. Especially for 22 nanometers, Intel claims that it became clear early on that continued shrinking was not going to give the expected benefits without some radical redesign. After a decade of research and development, taking advantage of the work of Hisamoto and others in FinFET development and optimization, Intel invented the solution. For the first time in history, the transistor has officially entered the 3rd dimension. Image 1 shows what a 3D transistor looks like.

Image 1: A 3D transistor chip

In fact, there are more than a billion transistors on this single chip which, unfortunately, are far too small to be seen with the naked eye. Now imagine yourself 20,000 times smaller! To give you a point of reference, right now, you are even smaller than a human hair. But you would actually still be far too large when compared to a 22 nano-meter transistor for a meaningful imagination. You actually need to be 100 nano-meters tall or about 20 million times smaller than your actual size. At this scale, you are about the right size to literally see, demonstrate some of the attributes and functions of a single, modern transistor out of those millions of transistors inside the 3D transistor chip. Well, since there's no such shrinking device as yet, let us just consider the figures below as transistors models and understand.

But first, what are 2-D transistors?

Image 2: Traditional Planar 2-D Transistor

For the last four decades, planar or 2-D transistors, have been at the core of transistor design and architecture. In the image-2, we see a form of silicon that creates a stream (dotted yellow) through which electrons flow. The gate, which is made of metal over a material with high dielectric constant, controls the flow of electricity in that stream. It acts as an ordinary switch, turning flow on and off. That is, if an ordinary switch had the ability to turn itself on and off over 100 billion times a second! Technically, traditional 2-D planar transistors form a conducting channel in the silicon region under the gate electrode when in the “on” state. Talking about states, some key objectives in transistor design are to have as much current flowing as possible when in the “on state” for performance, to have as close to zero current flowing when it is in the “off” state to minimize power usage, and to switch very quickly between the two states again, for performance.

Now Coming to 3-D Transistors...

Image 3: 22nm Trigate Transistor

As transistors get ever smaller, one way to achieve this is to get tighter control, by having the gate wrap around the channel as much as possible. The animated version of the transistor can be seen in image-3. With Intel's 3D transistor's architecture, the flat two dimensional stream has been replaced with one or more three-dimensional fins as shown in the image-4.

Image 4: 22nm Trigate Transistor

The control is on all the three sides of each fin, rather than just one, as in the the Planar 2-D transistor. In simpler terms, the transistor channel is raised into the 3rd dimension. Current flow is controlled on three sides of the channel (top,left and right). This is called a Tri-Gate transistor and its real advantage over Planar is the ability to operate at lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency. This breakthrough invention allows Intel to create transistors that are smaller, faster and use less power than ever before, enabling a new generation of computing technology in every category, from the fastest super computers to the smallest hand-held devices. Tri-Gate transistors can have multiple fins (as shown in image 5) connected together to increase total drive strength for higher performance.

Image 5: Tri-Gate transistors with multiple fins

The Real Deal With 3D
The 3-D geometry and structure of the Tri-Gate transistor provides a host of important improvements over the planar transistor structure, all related to the ‘wrap-around’ effect of the MOSFET ‘gate’ around the source-to-drain ‘channel.’ These advantages manifest in improved performance, reduced active and leakage power, transistor design density, and a reduction in transistor susceptibility to charged particle single event upsets (SEU).

The power advantage results from the improved control of the channel by the gate’s electric field on three sides of the fin. As explained by Intel Corporation at their Intel Developer Forums (2011, 2012), this power advantage is created by an effectively steeper transistor voltage curve for Tri-Gate transistors. Transistor designers can take advantage of this steeper curve with either a significant reduction in leakage current for the same performance of a planar transistor, or substantially higher performance (transistor operation speed), or a combination of both.

The Real Advantage of Tri-Gate Transistors
·More than 50% power reduction at constant performance.
·37% performance increase at low voltage.
·Improved performance and efficiency.

"For years we have seen limits to how small transistors can get," said Gordon E. Moore. "This change in the basic structure is a truly revolutionary approach, and one that should allow Moore's Law, and the historic pace of innovation, to continue." - Gordon E. Moore

"The performance gains and power savings of Intel's unique 3-D Tri-Gate transistors are like nothing we've seen before. This milestone is going further than simply keeping up with Moore's Law. The low-voltage and low-power benefits far exceed what we typically see from one process generation to the next. It will give product designers the flexibility to make current devices smarter and wholly new ones possible. We believe this breakthrough will extend Intel's lead even further over the rest of the semiconductor industry." - Mark Bohr, Intel Senior Fellow

Tri-Gate Devices Now in Production

Image 6: 22nm Manufacturing Fabs

The advanced state of semiconductor manufacturing at very small geometries (40 nm, 28 nm, 22 nm or 20 nm and beyond) requires research and development expenditures that now limit this technology to a handful of companies with capital expenditure capabilities in the billions of dollars. As a result, only a handful of manufacturers are able to capitalize on the known advantages of 3-D transistor technology. Intel Corporation is the only company to have made this design and manufacturing transition in 22 nm technology, and can provide data on the overall maturity and manufacturability of Tri-Gate transistors on a mass production scale. This data, as of the first quarter of 2013, includes 100 million units of Tri-Gate transistorbased products.

Image 7: Gates and Fins of 22 nm 3-D transistor

Several known issues and characteristics of the 3-D gate structure have been acknowledged and addressed to achieve manufacturing and design maturity with the technology. These include the modeling of new parasitic capacitance values not modeled in traditional planar designs, layout dependent effects, and the use of double-patterning techniques using current lithographic equipment to form closely spaced fins. A great deal of publicity and user education is underway in 2013 by companies like Cadence and Synopsys revolving around the impact of Tri-Gate rules and flexibility in the design of future semiconductor products.

Impact on FPGA and Other Semiconductor Device Performance

Let's see how this three dimensional technology will provide a significant boost in the capabilities of high-performance programmable logic.

The primary advantage of Tri-Gate technology to FPGA-based electronic product designer is the continuation of Moore’s Law in the steady march of improvements in transistor density, performance, power, and cost-per-transistor. This sustains an industry of consumer electronics, computing platform development, software complexity advances, memory and storage growth, mobile device creativity and development, and business automation and productivity.In addition, control over the static and active power dissipation of semiconductors improves tremendously with this technology. For users of FPGAs, this makes programmable logic that advances to 14 nm technology and beyond both power competitive with ASIC and ASSP design solutions on available competing design nodes, with even more significant advantages in programmability, performance, flexibility, Open Computing Language (OpenCL™) software design entry, and integration of DSP, transceiver, hardened processor, and configurable I/Os.


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How Torrent works

Posted by T P Kausalya Nandan
T P Kausalya Nandan
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on Monday, 10 February 2014
in Lets Know Things BETTER 0 Comments
How It Works?
Now, it’s time to see how the software is fetching the data. The torrent file works on the method of peer to peer sharing downloading method i.e. file is downloaded in different pieces according to their availability. To understand this downloading scheme, let’s go through the following steps:
1). The server consists of the data which a user wants to download. Let us assume that you want to download a movie.
Torrent Server
2). The file is being present on the server and is being getting downloaded by different computers in different parts earth. As well as there are also computers which already have finished downloading the movie. Now as stated above, the different computers consists of different pieces of same file. Like a user in North America have completed downloaded first half an hour of the movie and another person in Srilanka have downloaded some middle part of the movie. Similarly single file from server is getting downloaded between different users in pieces.  So, every user has some part of the file.
Torrent Server to Computer
3). Now it’s your turn to download the file, the software you have installed will scan or track the computers that have pieces of the file or complete file and starts downloading from that computer’s hard drive. In simple language, the computer consisting of pieces of file acts as the server for your computer. The file is downloaded in pieces from different computers hence the bandwidth is greatly reduced.
Torrent Computer to You
4). The speed of download depends upon the number of computers that are ON and downloading the file. AND the computers that have finished the downloading should seed the data so that others can download it.

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A Robot That Cooks Japanese Okonomiyaki Pancakes...!!

Posted by T P Kausalya Nandan
T P Kausalya Nandan
T P Kausalya Nandan has not set their biography yet
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on Monday, 10 February 2014
in Technology 0 Comments


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