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Center for VLSI Design was established in 2007 in Electronics & Communication for imparting a state-of the- art education, training and research in the field of VLSI Design. The Center offers a Master's programme in VLSI System Design with an intake of 36 students each. CVD has a faculty strength of 6, student strength of around 72 and is headed by Dr.Ramesh Vaddi, Post Doc from Nanyang TU, PhD from IIT Roorkie.
M.Tech VLSI System Design:
• The center is equipped with state of art tools like Cadence, Synopsys and Xilinx etc.
Scope for Employment
• Placement in leading core companies like Synopsys, Xilinx, AMD, ARM,NXP,Conexant,Sasken,Motorola, Toshiba, Samsung,Analog Devices,Robert Bosch and Tata Elxsi
• All R & D Organizations’ involving Embedded System Design and Development of Embedded Software

R & D Activities

A reputation for excellence in research supported by a high caliber staff is reflected in the demand for entry to Padmasri Dr B V Raju Institute of Technology's programmes from high achieving students in core electronics field. Committed to excellence in fundamental research as well as the development of innovative technologies for the future, Department of Electronics and Communication offers a quality research training experience for its students. The Institute maintains its relevance to world-class research by linking with industry and business through local and international research networks by eminent Professors Dr. I.A Pasha and Dr.V.Ramesh.

Prof.Sanjay Dubey, Mr.I.B.K.Raju Mrs.A.Rajakumari and Mr.M.C.Chinnaiah are pursuing research in VLSI & Digital Design. It also encourages its researchers to participate in a wide range of international research collaborations. BVRIT's extensive network creates unique opportunities for conducting and supporting research, particularly in multi-disciplinary areas.


A high speed and area efficient Booth recoded Wallace tree multiplier for fast arithmetic circuits(2012)     See More Publications
Integrated Circuit Design Techniques for Modern Digital systems(2010)     See More Publications
    I A Pasha
    Professor & HOD
    Qualifications : BE, M.Tech, Ph.D (OU), Post Doc (Villanova, USA), MIEEE, MIET, MISTE
    Area of Specialization : Antennas, Microwaves & Radar
    Area of Intrest : Radar Signal Processing
    Teaching Experience : 24
    Contact : 9441255304
    Email : pasha.ia@bvrit.ac.in
    Sanjay Dubey
    Qualifications : M.Tech, (PhD), MIEEE, MISTE
    Area of Specialization : Robotics, VLSI, Wireless & Mobile Communications
    Area of Intrest : VLSI, Digital Design, FPGA & Robotics
    Teaching Experience : 14 Years
    Contact : 9440229740
    Email : sanjay.dubey@bvrit.ac.in
    Assistant Professor
    Qualifications : MTECH
    Area of Specialization : VLSI SYSTEM DESIGN
    Teaching Experience : 3
    Contact : 9705521982
    Email : ramarao.ch@bvrit.ac.in
    Balarama Krishnam Raju Indukuri
    Associate Professor
    Qualifications : M.Tech (VLSI System Design)
    Area of Specialization : VLSI Systems
    Area of Intrest : VLSI,Signal Processing ,Computer architecture
    Teaching Experience : 9
    Contact : 09701266779
    Email : balaram.indukuri@bvrit.ac.in
    M C Chinnaaiah
    Associate Professor
    Qualifications : M.Tech,(Ph.D)
    Area of Specialization : VLSI,ROBOTICS.
    Teaching Experience : 12
    Contact : 9030833885
    Email : chinnaaiah.mc@bvrit.ac.in
    T.Vasudeva Reddy
    Associate Professor
    Qualifications : M.Tech (Ph,D)
    Area of Specialization : vlsi system design
    Area of Intrest : Low power VLSI, Wireless
    Teaching Experience : 10
    Contact : 9492734890
    Email : vasu.tatiparthi@bvrit.ac.in
    Prabhakar Kapula
    Qualifications : M.Tech (Ph.D), FIETE,MIEEE,MISTE
    Area of Specialization : Communication Systems
    Area of Intrest : Wireless Communications, Networked Control systems and Robotics
    Teaching Experience : 14
    Contact : 9885343147
    Email : prabhakar.kapula@bvrit.ac.in
    Qualifications : M.Tech(Ph.D)- VLSI SYSTEM DESIGN
    Area of Specialization : VLSI & EMBEDDED SYSTEMS DESIGN
    Area of Intrest : SOC,wireless Sensor Networks,Embedded System,Robotics
    Teaching Experience : 6
    Contact : 9032740752
    Email : gangaprasad.t@bvrit.ac.in
    Jayshree Das
    Associate professor
    Qualifications : M.Tech, (Ph.D),MISTE
    Area of Specialization : VLSI
    Area of Intrest : VLSI, FPGA, RADAR signal processing
    Teaching Experience : 14 years
    Contact : 8985306160
    Email : jayshree.das@bvrit.ac.in




I YEAR   - I Semester

I YEAR   - II Semester

Microcontrollers for Embedded System Design

Embedded real time operating systems

CPLD & FPGA Architectures and Applications

Low power VLSI Design

VLSI Technology & Design

DSP Processors and Architectures

Algorithms for VLSI Design Automation

System –on-Chip Architecture

Digital System Design

CMOS Analog & Mixed signal design

Advanced Digital Signal Processing

Design of Fault Tolerant Systems

Simulation Lab (VLSI)

Embedded System Lab (VLSI)



II YEAR   - I Semester

II YEAR   - II Semester

Comprehensive Viva Voce & Dissertation Work





Center for VLSI Design
The lab is  a part of I Year M.Tech I & II Semester and is equipped with state of art Cadence, Synopsys & Xilinx Tools to implement Analog & Digital ICs.
XILINX-CPLD and FPGA Kits are used for implementation of Verilog code. It is equipped with 20 Personal Computers.


Department Library responds to the varying needs of the academic community by involving the faculty, the students and the administration in the development and periodic assessment of the library services and resources.It also provides library users with point of use instruction, personal assistance in conducting literature research and making accessible to collection of printed and non printed material

S.No Name of the Student Roll No. Percentage
 2012 Passed outs

 2011 Passed outs


 2010 Passed outs


2009 Passed outs



Professional Bodies:

• IEEE Students' Chapter (Institution Electrical & Electronics Engineering)
STE (Indian Society for Technical Education) Students' Chapter
• Electronics Students Association Activities


Thursday, 26 April 2012 by Administrator

A Parents meeting was organized for II-B.Tech-ECE at BVRIT CITY CENTER, Panjagutta, Hyderabad on 20th February 2011 from 10 am to 3.30 pm.


Around 35 students from II B.Tech (2009-13 batch) were identified as academically weak students by the advisory committee of Dept.The parents of all the students identified were invited to the meet by the class In charges and counselors.

Parents of 27 students from II B.Tech have attended the meet and were counseled by Dr.I.A.Pasha & Mr.Sanjay Dubey. The parents of remaining 08 students have expressed their willingness to come to college & meet us.

We suggested some measures to the students as well as their parents to improve their ward's academics and also how to clear the backlogs before 3-2 sem, So that they are eligible for placements. They were also advised to ensure that their wards attend the remedial classes that are going to be arranged for them.We also inquired about tuition fees dues if any with parents.

Parents gave suggestions to conduct Group discussions & Communication skills for their students during II year onwards.

We have taken Photos & also videos of parents opinion about college and Dept. which I will send it by tomorrow.

A feedback form & an undertaking was also collected from parents for students who fall shortage of attendance.

The following faculty members were present:

Dr.I.A.Pasha,HOD ECE Department

Mr.Sanjay Dubey, Asso.Prof. & Dept.Coordinator

Mr.M.C.Chinnaiah, Asso.Prof.,

Mr.Harikrishna, Asst.Prof. & II ECE-B Class Incharge.

Mrs.Jayshree Das, Asst.Prof. & II ECE-A Class Incharge.



Parents and teachers share a common treasure—the student.

To develop the communication that will allow parents and teachers to make plans, set goals, solve problems, and establish the relationship that they need in order to have a good partnership, a Parent-Teacher Meeting is required.

Parents meet helps to communicate to parents the areas their children are excelling in and the areas their children are weak and to give them specific ideas of how to improve upon their child’s performance.

Parents meet should be used as a platform to make a lasting bond with the parent to increase the likelihood of academic success for their child.

Keeping this goal in mind, a Parents meeting was organized in the BVRIT CITY CENTER, Panjagutta, Hyderabad on today the 19th September 2010 from 11am to 5 pm.

To organize the meeting joint efforts were made by all the faculty members of Department of Electronics & Communication engineering.

A meeting with faculty members was organized and an advisory committee was formed under the chairmanship of Dr.I.A.Pasha, Head of the department of ECE.

We have identified 25 students from III B.Tech (2008-12) and 40 students from IV B.Tech (2007-11) as academically weak students (a copy is attached here with).

The parents of all the students identified were invited to the parents meet by the mentors (faculty members) concerned.

Parents of 11 students from III B.Tech and 11 students from IV B.Tech were attended the meet (find attached the copy).

The parents as well as students were counseled by the mentors concerned and the advisory committee headed by Dr.I.A.Pasha.

Vice chairman Sri Ravichandran Rajagopal also joined with advisory committee in the afternoon session. He also encouraged the steps taken by the ECE department to improve the academics.

Dr.Pasha also suggested some measures to the students as well as their parents to improve the academics. The parents were given some guidelines to follow to improve the academics of their son / daughter.

Parents asked several queries regarding the performance of their son/daughter and the doubts raised by them were clarified by mentors and HoD.

Also a feedback form was designed in order to take feedback of parents on the Faculty members, teaching, infrastructure, canteen, transportation etc. All the parents were given this feedback form to be filled.



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