Cyient Incubation Centre

Objective of this center is to create academic center of excellence in semiconductor technology. The key activities of the above center is to provide domain training by VLSI experts from CYIENT to students supported by two faculty members Mr.I.B.K Raju and U. Gnaneshwara chary from Dept of Electronics and communication, BVRIT who also got trained by CYIENT. Training is followed by Identify the real time problems and finding the technological solutions and validating the idea (proof of concept). Once the idea is formulated and validated design and implementation will be proceeded.

Major Hardware / Software

S.No Major Hardware / Software
1 HP Computers
2 VERTEX 5
3 SPARTON 3E, 3A
4 SYNOPSYS EDA Tools for ASIC Solutions
5 XILINX ISE

OUTCOMES ACHIEVED

With the Establishment of BVRIT-CYIENT Incubation Center we achieved new heights by training the students at Industrial level of VLSI Knowledge set. Center played an important role in placement & internships of B.Tech students. The following students are benefited in Placement and Internships.

S.No Student Name Company Placed in
1 MANASA SAROVARI GGK Technologies / Soctronics
2 ANJALI TECHMAHINDRA
3 ASHWINI TECHMAHINDRA
4 ANWAR KHAN TECHMAHINDRA
5 VASAVI SREEJA TECHMAHINDRA
6 VIBHUTI TECHMAHINDRA
7 VIDEESHA TECHMAHINDRA
8 BHAVYA REDDY CAPGEMINI
9 GAYATHRI CAPGEMINI
10 PRAVALIKA CAPGEMINI
11 SHIVANI CAPGEMINI
12 VENKATA KISHORE CAPGEMINI / ADEPT CHIPS
13 JOHN CAPGEMINI
14 PREM CHAND ADEPT CHIPS
15 BHUVANESHWARI NTT DATA

BATCH-II

TRAINING PHASE

Details of the Training Details of Resource Persons Date & Time Duration No. of Students Benefited Remarks
  CYIENT Industrial Experts:      
6-Months Hands on Training Program on VLSI Design Avinash Yedlapati, Project Manager 18/07/16 to 31/12/16 24 UG Students Completed Successfully
  Mandeep Singh, Project Lead      
  Vineeth Tandon, Assistant Project Manager      
  Prasad Raju, Assistant Project Manager      
  Lingaiah Bontha, Team Lead      
  Vinay, Associate Engineer      
  BVRITN Academic Experts:      
  I.B.K.Raju, Assoc Prof, ECE Dept      
  U.Gnaneshwara Chary, Asst Prof, ECE Dept      

PROJECT PHASE

Details of the Activity Title of Project Date & Time Duration No. of Students Benefited Remarks
Ideation & Brain Storming ASIC Implementation of NAND Flash Controller 1/3/16 to 31/3/16 21 (17 UG+4 PG) Completed Successfully
RTL Design ASIC Implementation of NAND Flash Controller 4/7/2016 to 30/9/2016 21 (17 UG+4 PG) Completed Successfully
RTL Verification ASIC Implementation of NAND Flash Controller 1/10/2016 21 (17 UG+4 PG) Completed Successfully

TRAINING PHASE

Faculty Training

Training Details: 4-Month Faculty Training Program
Dates: 2/11/15 to 29/2/16
Venue CYIENT Ltd ,Hyd
No. of Students Benefited: 2 (I.B.K.Raju, Assoc Prof & U.Gnaneshwara Chary, Asst Prof )
Status of Training sessions: Completed Successfully

Student Training

Training Details: 3-Months Hands on Training Program on VLSI Design
Dates: 2/12/15 to 29/2/16
No. of Students Benefited: 21 (17 UG+4 PG)
Status of Training sessions: Completed Successfully

Training Details

Date Topics covered Resource Persons
02/12/2015 ASIC/FPGA Design Flow Mr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
03/12/2015 to 05/12/2015 Exercises on Digital and Advanced Digital Designs I.B.K. Raju &Gnaneshwara chary
07/12/2015 FSM Design Mr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
09/12/2015 to 12/12/2015 Exercises/Labs on Verilog/State Machines/System Verilog I.B.K. Raju &Gnaneshwara chary
14/12/2015 Verification Mr. Vineet, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
16/12/2015 to 19/12/2015 Exercises/Labs on writing effective Testbenches I.B.K. Raju &Gnaneshwara chary
22/12/2015 to 26/12/2015 Exercises/Labs on RTL Code and Testbenches with Code Coverage options I.B.K. Raju & Gnaneshwara chary
28/12/2015 Synthesis Mr. P. Madhan Mohan,Team Lead, CYIENT, Mr. B.Lingaiah, Team Lead, CYIENT
29/12/2015 to 05/01/2016 Exercises/Labs on Synthesis of Digital Circuits I.B.K. Raju & Gnaneshwara chary
07/01/2016 System Verilog verification Methodology Mr. Vineet, Manager, CYIENT, HYD
20/01/2016 Logic Equivalence Checking & Static Timing Analysis Mr. P. Madhan,Team Lead, CYIENT, Mr. P. Bhargava, Team Lead, CYIENT
21/01/2016 to 23/01/2016 Exercises/Labs on LEC I.B.K. Raju & Gnaneshwara chary
28/1/2016 Physical Design Mr. K.Madhusudan Rao, Project Manager,CYIENT, HYD, Mr. Konda Reddy, Tech lead, CYIENT, HYD
04/02/2016 Analog Layout Design Mr. Raja Randham, Layout Manager, CYIENT, HYD, Mr. Vishnu, Layout Engineer, CYIENT, HYD
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