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EAMCET| ICET| ECET| CODE: BVRI| PGECET| CODE: BVRI1

Welcome to BVRITN

Center for VLSI Design

Faculty Coordinator:Mr. K. Madhava Rao

Faculty Members:U.Gnaneshwara Chary,  Ananda Kumar, Ramesh Reddy, Yeshwanth

Major Hardware / EDA Tools

S.No Major Hardware / Software
1 >SYNOPSYS TOOLS
2 XILINX ISE 14.4
3 XUPV5-LX110T BOARD
4 SPARTAN 3A XC3SD1800 DSP STARTAN KIT
5 SPARTAN2 XC2S100 FPGA

SERVER

S.No Major Hardware / Software
6 POWERED BY LINUX SERVER
7 HP PROLIAN ML 150 G5 SERVER,QUAD- CORE INTEL XEON
8 HP 19 “ TFT MONITOR

NETWORK CONNECTION NODES

9 HP DX 2480 DESKTOPS
10 INTEL PENTIUM CORE2 DUO E4600
11 1 GB RAM PX976,320 GB HDD, HP DVD RW
12 969 SATA KEY BOARD /MOUSE, 19”TFT MONITORS

DATA SWITCH

13 10/100 FAST ETHERNET SWITCH 24 PORTS
14 D-LINK DES-1024D

ELECTRICAL EQUIPMENT

15 10 KVA UPS HALF AN HOUR BACKUP

. This Lab exposes the students to latest in IC Design Technology. The main objective of the center is to enabling the excellence in training for VLSI Technology and to bridge the gap between academic and VLSI industry.

CVD-Workshops

S.No Details of the Workshop Details of Resource Persons ( In-house/Industry) Time Duration Academic Year No. of Students Benefited
1 Design For Testability, Industrial Practices Mr. I. B. K. Raju, DFT Engineer, Sankalp Semiconductor Pvt.Ltd. Bangalore. S1: 28-12-19 , S2: 10-01-2020, S3: 25-01-2020, S4: 01-02-2020 2019-20 40
2 Asic Design Using Synopsys Tools Mr. Praveen Kumar- Application Engineer, A.S. Varun- Regional Manager. 14th- 19th OCT-2019 2019-20 30
3 Advanced Digital Design using Verilog HDL Mr.Raja Bandi, Director, LUCID VLSI, Hyderabad 17th to 20th and 22nd December 2018 2018-19 30
4 Advanced Digital Design using Verilog HDL Mr.Raja Bandi, Director, LUCID VLSI, Hyderabad 20-23rd July 2017 at BVRIT, Narsapur. 2017-18 33
5 Introduction to UMA Processor and Simulator Mr. Rajasekhar, Mr. Usha Kiran 10-01-2017 to 13-01-2017. 2016-17 13
5 VLSI Design Flow using SYNOPSYS Tools SYNOPSYS, Hyd and EIGEN Technologies, New Delhi 29th December 2015 -2nd January 2016 2015-16 30
6 VLSI & Embedded Design Flow using XILINX ZYNQ SOC XILINX,Hyd, Coreel Technologyes, Hyd, IEEE, Hyd 9th-11th March 2015 2015-16 30

Guest Lectures

S.No Title of the project Details of Resource Persons ( In-house/Industry) Time Duration Academic Year No. of Students Benefited
1 Dynamic and Static Timing Analysis Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 08/07/2020 2019-20 36
2 Metastability in Front end design Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 11/07/2020 2019-20 36
3 Metastability in Front end design, cont.... Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 18/07/2020 2019-20 36
4 Clock Domain Crossing Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 25/07/2020 2019-20 36
5 Static Timing Analysis Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 13/06/2020 2019-20 36
6 Digital Synthesis Flow in VLSI Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 13/06/2020 2019-20 36
7 Digital Synthesis Flow with Low Power in VLSI( Five day STTP on Low Power VLSI) Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 20/06/2020 2019-20 36
8 Industry approach for VLSI Front End Design Problem Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 27/06/2020 2019-20 36
9 Polymorphism Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 03/03/2020 2019-20 36
10 Randomizing Objects Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 07/03/2020 2019-20 36
11 Random Variables Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 14/03/2020 2019-20 36
12 Industrial approach in front end design Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 22/05/2020 2019-20 36
13 OOPS concept in System verilog Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 04/02/2020 2019-20 36
14 Class, Object Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 15/02/2020 2019-20 36
15 Inheritance, Abstraction Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 20/02/2020 2019-20 36
16 Encapsulation Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 25/01/2020 2019-20 36
17 Verification Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 04/01/2020 2019-20 36
18 Introduction to System Verilog Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 10/01/2020 2019-20 36
19 Data Types Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 23/01/2020 2019-20 36
20 Arrays Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 25/01/2020 2019-20 36
21 Synthesis Flow Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 07/12/2019 2019-20 36
22 Static Timing Analysis using Prime Time Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 11/12/2019 2019-20 36
23 Functional/Gate Simulation and Verification Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 20/12/2019 2019-20 36
24 Physical Verification and Extraction. Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 28/12/2019 2019-20 36
25 M.Tech Projects Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 26/04/2018 2017-18 11
26 M.Tech Projects Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 19/04/2018 2017-18 11
27 Verilog Constructs Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 13/04/2018 2017-18 22
28 Verilog Programming Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 06/04/2018 2017-18 71
29 B.Tech and M.Tech Project Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 31/03/2018 2017-18 45
30 Interaction with M.Tech Students Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 24/03/2018 2017-18 14
31 Verilog Concepts discussion with II-ECE-B Students Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 09/03/2018 2017-18 71
32 Verilog Programming and Test Benches Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 03/03/2018 2017-18 26
33 Workshop on ASIC Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 23/02/2018 2017-18 52
34 Workshop on ASIC Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 17/02/2018 2017-18 52
35 FPGA Architectures Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 10/02/2018 2017-18 38
36 FPGA Design Flow Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 06/02/2018 2017-18 26
37 Finite State Machines Mr. Avinash Yadlapati, Senior Director, Mirafra Technologies 20/01/2018 2017-18 26

Participation in contests by Students

S.No Name of the Contest Place No. of Students Academic Year
1 Sankalp Hackathon Admas University,Kolkata 2 2019-20
2 L& T Techgium Bangalore 2 2019-20
3 NASA Space App Challenge New Delhi 2 2019-20
4 DST & Texas Instruments India Innovation Challenge Design Contest 2018 IIM, Bangalore 4 2018-19
5 Startup India MHRD, Hyderabad 2 2018-19
6 Synopsys India 2017 Custom Design Contest Synopsys India Pvt. Ltd., Uttar Pradesh 2 2017-18
7 Synopsys India 2016 Custom Design Contest Synopsys India Pvt. Ltd., Uttar Pradesh 2 2016-17

Certifications done by Students

S.No Certificate from Number of Students Certified
1 Amazon Web Services 1
2 Cisco 1
3 CITD, Hyd 9
4 Cognitive class 5
5 Coursera 87
6 Google 1
7 Guvi 1
8 HackerRank 1
9 ICSI 1
10 Jigsaw 5
11 Mentor Graphics 6
12 NASSCOM 3
13 NEO Organization 1
14 NPTEL 5
15 PIRPLE 1
16 Simplilearn 13
17 Tata Steel 1
18 TCS 3
19 Udemy 3

Placements in Core Industries

S.No Roll Number Name of the Student Company Placed Academic Year
1 16211A0403 Himavanth SilinConch

2019-20

 

2 16211A0405 Ramsai Reddy VEDA IIT
3 16211A0456 Prathibha VEDA IIT
4 16211A04N3 Sandeep VEDA IIT
5 16211A0401 Rakesh HYSOC Technologies
6 16211A0405 Ram Sai Reddy HYSOC Technologies
7 16211A04B4 Jyotsna HYSOC Technologies
8 16211A04M9 Mahesh Babu HYSOC Technologies
9 17211D5703 Ismat Amreena Juntran
10 17211D5711 Gopa Sowmya Juntran
11 17211D5706 Prashamsa SiliConch
12 15211A04F4 JAYENDRA PRASAD HYSOC Technologies 2018-19
13 15211A04G6 R TEJASWINI HYSOC Technologies
14 15211A0437 PRASHANTH KUMAR HYSOC Technologies
15 15211A04H2 P GOUTHAM HYSOC Technologies
16 15211A0498 SAI RAM PRAKASH HYSOC Technologies
17 16215A0417 USHA RANI HYSOC Technologies
18 15211A04F4 JAYENDRA PRASAD SOCTRONICS (VEDA IIT)
19 15211A0494 PRASHANTH KUMAR SOCTRONICS (VEDA IIT)
20 15211A04H2 P GOUTHAM SOCTRONICS (VEDA IIT)
21 15215A0403 HIMAVANTH Ferventz Semi-Conductors
22 15211A0410 ARSHIVA Ferventz Semi-Conductors
23 15215A0416 PRAVALLIKA Ferventz Semi-Conductors
24 15211A04E2 SRI DEVI Ferventz Semi-Conductors
25 15211A04E7 ASHRITH Ferventz Semi-Conductors
26 15211A04G0 CHANDANA Ferventz Semi-Conductors
27 15215A0443 DIWAKAR Ferventz Semi-Conductors
28 15215A0423 SHIVA PRASAD HYSOC Technologies 2017-18
29 14211A0487 CHANDANA HYSOC Technologies
30 14211A04H9 TEJASWINI HYSOC Technologies
31 14211A0429 SRUJAN HYSOC Technologies
32 14211A04D2 P SHRUTHI HYSOC Technologies
33 14211A04D5 SAI BHAVYA HYSOC Technologies
34 14211A0447 VYSHNAVI SOCTRONICS (VEDA IIT)
35 14211A0474 NAGA SRUJANA SOCTRONICS (VEDA IIT)
36 14211A04C6 SHARATH CHANDRA SOCTRONICS (VEDA IIT)
37 14211A0466 Hari Hara Naga Vamshi SOCTRONICS (VEDA IIT)
38 14211A0470 TRIPURA ADEPT CHIPS
39 14211A04E7 HARI TEJA ADEPT CHIPS
40 14211A0466 Hari Hara Naga Vamshi ADEPT CHIPS
41 14211A0421 MAHITHA ADEPT CHIPS
42 14211A04C4 GOPAL ADEPT CHIPS
43 14211A04F7 KRANTHI KUMAR ADEPT CHIPS
44 13211A0469 Manasa Sarovari VEDA IIT 2016-17
45 13211A04G6 Venkata Kishore Adept Chips
46 13211A0492 PremChand Adept Chips
47 14215A0433 Anil Kumar Adept Chips

Internships in Core Industries

S.No Roll Number Name of the Student Company Placed Academic Year
1 16211A04F7 Shailu HYSOC Technologies 2019-20
2 16211A0456 Pratibha HYSOC Technologies
3 16211A04E0 Sree Vidya HYSOC Technologies
4 16211A04G6 Naresh HYSOC Technologies
5 16211A0483 Rakesh K HYSOC Technologies
6 16211A0466 Sushmitha HYSOC Technologies
7 12211AD4 Shyam Sunder Reddy CYIENT, Hyd 2015-16
8 12211AD6 Siddartha Reddy CYIENT, Hyd
9 12211AC6 Sangameshwar CYIENT, Hyd
10 14211D5706 (M.Tech) B.Malathi Research Center Imarat (RCI) ,Hyderabad
11 14211D5713 (M.Tech) P.Shyamala Research Center Imarat (RCI) ,Hyderabad
12 14211D5710 (M.Tech) Sheri Mounika Smarttrak, Hyderabad
13 14211D5720 (M.Tech) T.Vishwa Tevatyron Technology, Noida
14 14211D5707 (M.Tech) R.Manikanta Manjeera Digital Systems
15 14211D5717 (M.Tech) Sushanth Reddy Manjeera Digital Systems
16 13211D5704 (M.Tech) Kavya Paruchuri Synopsys
17 13211D5708 (M.Tech) G.Abhishek Synopsys
18 13211D5709 (M.Tech) K.Akhila Synopsys
19 13211D5715 (M.Tech) M.Harish Kumar Synopsys
20 13211D5719 (M.Tech) Sai Kriranmayee Synopsys
21 11211A04A3 Kotha Rajesh Synopsys

Student - Faculty Publications 2019-20

U.Gnaneshwara chary, Poralla Divya, The International Journal of Analytical and Experimental Model Analysis “June 2020 Volume XII, issue VI, Pg. nos:1404-1410 Design and Implementation of VLSI architecture for Error correction and Detection.
U.Gnaneshwara chary, Goundla Priyanka The International Journal of Analytical and Experimental Model Analysis June 2020Vol ume XII, issue VI, Pg. nos:1388-1394 Low Quantum Cost Reversible Logic Gates and QCA Architectures. >
K.Madhava Rao,P. Rajesh, P. Akash, P.Pragath & M. Sai Mahesh The International Journal of Analytical and Experimental Model Analysis April-2020 volume XII,issue IV, Pg.nos :1957-1963 FPGA Based Robotic ARM Controller.
K.Madhava Rao, D. Sai Shradha, Ch. Kavya Madhuri, B. Ravi, D. SudheerInternational Journal of Research in Engineering, Science and Management April-2020 Volume 4, Issue 3, Pg.nos: 332-334 Implementation of ALU by Vedic Algorithm.
K.Madava Rao, International Journal of Recent Technology and Engineering (IJRTE) Jan-20 ISSN: 2277-3878, Volume-8, Issue-5,Design of FinFET based 128 bit SRAM in 7nm & various Effects near threshold operation for ultra low power application. Estimation in Connected Cars (SCOPUS).
T.Vasudeva Reddy, K.Madava Rao, P.Kavitha Reddy International Journal of Innovative Technology and Exploring Engineering (IJITEE) Dec-19 ISSN: 2278-3075, Volume-9 Issue-2, MEMS Design Techniques and Performance (SCOPUS).
C Ramesh Kumar Reddy, Syed Muqtar Nawaz, Sureddy Sravya, Mohammed Imran International Journal of Advance Research, Ideas and Innovations in Technology May 2020 ISSN: 2454-132X Impact factor: 6.078 Volume 6, issue 2 ASIC implementation of smart home using VLSI design.
J. Yeshwanth Reddy International Journal of Current Advanced ResearchApril-2020 Volume : 9 , Issue : 4 Implementation of I2C communication protocol with RTC and EPROM using FPFA.

Student - Faculty Publications 2018-19

A Low Power Analysis of Calibration Resistance Circuit Using DTMOS Logic- U. G. Chary, Bala Bandhavi, Naga srujana, Tripura..
GESTURE BASED HOME AUTOMATION SYSTEM USING SPARTAN 3A, ASIC International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 Scopus, K. Madhava Rao.
Dr. T.Vasudeva Reddy & K.MadhavaRao has presented a paper on "Novel strategies of Low power Subthreshold SRAM designs under 32nm for real-time applications." in InternationalConference on Computational and Intelligent Techniques for Automation of Engineering Systems (CITAES), Scopus Nov 30Th&1st December
Clock feed through problem reduction- U. Gnaneshwara chary, I.B.K Raju, Yeshwanth Reddy.
Design of parity generator and parity checker using QCA- U.G.Chary.
U-Turn Collision Caution System Using FPGA-(conference paper), U.Gnaneshwara chary, Tejaswini, Vishnavi Manda, Sharath Kumar..
K. Madhava Rao has presented a paper on “Performance & functionality of novel Subthreshold SRAM’s using low power techniques for SoC designs”in 3rd International Conference on Communication and Electronics Systems (ICCES 2018), 15th & 16th,,October 2018,Coimbatore,india.
K. Madhava Rao has presented a paper on “Design & comparative analysis of low power subthreshold source coupled logic (SCL) based SRAM with traditional SRAM under 32nm”in nternational Conference on Innovations in Engineering, Technology and Sciences” (ICIETS),20th & 21st September 2018 ,Mysore,India.
K. Madhava Rao, et al published paper on “Design, Simulation & Comparison Of Novel Tg8t SRAM With Traditional SRAM Design In Open Access International Journal Of Science & Engineering, Volume 2,Issuexii,December 2018||ISSN (Online) 2456-3293.(UGC approved)
Udari Gnaneshwara chary, J. Yeshwanth Reddy published a paper on Analysis of Clockfeedthrough and Chargeinjection using cadence 180nm Technology in International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 (Scopus Indexed)
Udari Gnaneshwara chary published a paper on A Low Power Analysis of Calibration Resistance Circuit Using DTMOS Logic in International Journal of Pure and Applied Mathematics Volume118 No. 24 2018 (Scopus Indexed)
Dr T. Vasudeva Reddy , K. Madhava Rao has presented a paper on “Design & comparative analysis of low power subthreshold source coupled logic (SCL) based SRAM with traditional SRAM under 32nm”in nternational Conference on Innovations in Engineering, Technology and Sciences” (ICIETS),20th & 21st September 2018,Mysore,India

Student - Faculty Publications 2017-18

K. Madhava Rao, et al published paper on “Design & comparison of novel low power, sub threshold Schmitt trigger based SRAM & source coupled logic for cognitive applications. In Open Access International Journal of Science & Engineering, Volume 2, Issue , November 2017||ISSN (Online) 2456-3293.
K. Madhava Rao, et al published paper on “Design & Analysis of Single Bit Sub-Threshold SRAM using Traditional SRAM Design under 32nm Design” Volume 5, Issue XI, November 2017,in International Journal for Research in Applied Science & Engineering Technology.

BVRIT - Cyient Incubation Centre

Objective of this center is to create academic center of excellence in semiconductor technology. The key activities of the above center is to provide domain training by VLSI experts from CYIENT to students supported by two faculty members Mr.I.B.K Raju and U. Gnaneshwara chary from Dept of Electronics and communication, BVRIT who also got trained by CYIENT. Training is followed by Identify the real time problems and finding the technological solutions and validating the idea (proof of concept). Once the idea is formulated and validated design and implementation will be proceeded.

BATCH-II

TRAINING PHASE

Details of the Training Details of Resource Persons Date & Time Duration No. of Students Benefited Remarks
 6-Months Hands on Training Program on VLSI Design         CYIENT Industrial Experts:  18/07/16 to 31/12/16          24 UG Students          Completed Successfully        
Avinash Yedlapati, Project Manager
Mandeep Singh, Project Lead
Vineeth Tandon, Assistant Project Manager
Prasad Raju, Assistant Project Manager
Lingaiah Bontha, Team Lead
Vinay, Associate Engineer
BVRITN Academic Experts:
I.B.K.Raju, Assoc Prof, ECE Dept
U.Gnaneshwara Chary, Asst Prof, ECE Dept

PROJECT PHASE

Details of the Activity Title of Project Date & Time Duration No. of Students Benefited Remarks
Ideation & Brain Storming ASIC Implementation of NAND Flash Controller 1/3/16 to 31/3/16 21 (17 UG+4 PG) Completed Successfully
RTL Design ASIC Implementation of NAND Flash Controller 4/7/2016 to 30/9/2016 21 (17 UG+4 PG) Completed Successfully
RTL Verification ASIC Implementation of NAND Flash Controller 1/10/2016 21 (17 UG+4 PG) Completed Successfully

TRAINING PHASE

Faculty Training

Training Details: 4-Month Faculty Training Program
Dates: 2/11/15 to 29/2/16
Venue CYIENT Ltd ,Hyd
No. of Students Benefited: 2 (I.B.K.Raju, Assoc Prof & U.Gnaneshwara Chary, Asst Prof )
Status of Training sessions: Completed Successfully

Student Training

Training Details: 3-Months Hands on Training Program on VLSI Design
Dates: 2/12/15 to 29/2/16
No. of Students Benefited: 21 (17 UG+4 PG)
Status of Training sessions: Completed Successfully

Training Details

Date Topics covered Resource Persons
02/12/2015 ASIC/FPGA Design Flow Mr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
03/12/2015 to 05/12/2015 Exercises on Digital and Advanced Digital Designs I.B.K. Raju &Gnaneshwara chary
07/12/2015 FSM Design Mr. Avinash, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
09/12/2015 to 12/12/2015 Exercises/Labs on Verilog/State Machines/System Verilog I.B.K. Raju &Gnaneshwara chary
14/12/2015 Verification Mr. Vineet, Manager, CYIENT, HYD, Mr. Mandeep Team Lead,, CYIENT, HYD
16/12/2015 to 19/12/2015 Exercises/Labs on writing effective Testbenches I.B.K. Raju &Gnaneshwara chary
22/12/2015 to 26/12/2015 Exercises/Labs on RTL Code and Testbenches with Code Coverage options I.B.K. Raju & Gnaneshwara chary
28/12/2015 Synthesis Mr. P. Madhan Mohan,Team Lead, CYIENT, Mr. B.Lingaiah, Team Lead, CYIENT
29/12/2015 to 05/01/2016 Exercises/Labs on Synthesis of Digital Circuits I.B.K. Raju & Gnaneshwara chary
07/01/2016 System Verilog verification Methodology Mr. Vineet, Manager, CYIENT, HYD
20/01/2016 Logic Equivalence Checking & Static Timing Analysis Mr. P. Madhan,Team Lead, CYIENT, Mr. P. Bhargava, Team Lead, CYIENT
21/01/2016 to 23/01/2016 Exercises/Labs on LEC I.B.K. Raju & Gnaneshwara chary
28/1/2016 Physical Design Mr. K.Madhusudan Rao, Project Manager,CYIENT, HYD, Mr. Konda Reddy, Tech lead, CYIENT, HYD
04/02/2016 Analog Layout Design Mr. Raja Randham, Layout Manager, CYIENT, HYD, Mr. Vishnu, Layout Engineer, CYIENT, HYD